The basic construction of a nonvolatile memory device is illustrated in FIG. 1.
The memory device shown in FIG. 1 is a flash memory, and contains a memory cell array SZF having a multiplicity of memory cells which are arranged in a multiplicity of rows and in a multiplicity of columns, each of the memory cells being performed by a memory transistor and being designed for storing a single bit.
The memory cell array SZF contains n memory cell columns SS1 to SSn and m memory cell rows SR1 to SR4, where n and m are greater than or equal to 1.
The memory transistors are designated by the reference symbols T11 to Tnm and each have a gate section with a gate terminal G, a drain section with a drain terminal D, a source section with a source terminal S, and a floating gate FG. The construction and the method of operation of such memory transistors are known, so that a more detailed description thereof can be dispensed with.
The source terminals S of the memory transistors of each memory cell column SS are in each case connected via a source line SL1, SL2, . . . , SLn to ground or any other voltage; for the sake of completeness, it should be noted that of the source lines SL1, SL2, . . . , SLn present, a plurality or all of the source lines can be connected to one another. The drain terminals D of the memory transistors of each memory cell column SS are in each case connected to one another via a bit line BL1, BL2, . . . BLn. The gate terminals G of the memory transistors of each memory cell row SR are in each case connected to one another via word lines WL1, WL2 . . . WLm.
Furthermore, the arrangement shown in FIG. 1 contains a sense amplifier SA1, SA2, . . . SAn per bit line, the sense amplifier SA1 being connected to the bit line BL1 on the input side, the sense amplifier SA2 being connected to the bit line BL2 on the input side, . . . , and the sense amplifier SAn being connected to the bit line BLn on the input side. For the sake of completeness, it should be pointed out that provision may also be made of fewer sense amplifiers, for example only half as many sense amplifiers, and the sense amplifiers present may alternately be connected to different bit lines via multiplexers or the like.
Flash memories furthermore generally contain a page memory, in which the data that are to be written simultaneously to the flash memory are buffer-stored. Furthermore, a control device which controls the erasure, programming and read-out of the flash memory is generally provided. The page memory and the control device are not illustrated in FIG. 1.
The level of the bit stored in a memory cell depends on the charge state of the floating gate FG of the memory transistor forming the relevant memory cell. Said charge state, to put it more precisely the quantity of free electrons present in the floating gate, can be altered by erasure or programming of the relevant memory cell and does not alter or alters at most to an extremely small extent after the erasure or programming. Dependent on the charge state of the floating gate is the threshold voltage of the relevant memory transistor, that is to say the difference between the voltage applied to the source terminal and the voltage applied to the gate terminal, from which the memory transistor undergoes transition from the off state to the on state or from the on state to the off state.
During the erasure and programming of a memory cell, the memory transistor forming the relevant memory cell is driven by application of corresponding voltages to the gate terminal, the source terminal and the drain terminal in such a way that the number of free electrons present in the floating gate of the memory transistor is increased or reduced. To put it more precisely, voltages applied to the gate terminal, the source terminal and the drain terminal are such that electrons present in the floating gate migrate to the source section via an insulating layer present between the floating gate and the source section, or that electrons migrate from the source section to the floating gate via the insulating layer. The specific way in which this occurs is known and does not require more detailed explanation.
In the example under consideration, as a result of the erasure of a memory cell, the number of electrons present in the floating gate is reduced, and the level of the bit stored in an erased memory cell is defined as 0. It should be apparent and needs no explanation that there is not any restriction to this. It is also possible for the number of electrons present in the floating gate to be increased as a result of the erasure of a memory cell. Independently of how the memory cell is erased, it is also possible, of course, to define the level of the bit stored in an erased memory cell as 1.
The programming of a memory cell is carried out in such a way that the opposite procedures take place. That is to say, in the example under consideration, the number of electrons present in the floating gate is increased as a result of the programming of a memory cell. If the number of electrons present in the floating gate is increased as a result of the erasure of a memory cell, the number of electrons present in the floating gate is reduced as a result of the programming of this memory cell. The level of the bit stored in a programmed memory cell is defined complimentarily with respect to the level of the bit stored in an erased memory cell.
For the sake of completeness, it should be noted in this connection that a memory cell of a flash memory, as a result of it being programmed, can only be brought to a state which is complementary to the erased state of the memory cell. That is to say, in the case of flash memories, as a result of a programming, either a bit having the value 1 can only be written to a memory cell storing a bit having the value 0, or a bit having the value 0 can only be written to a memory cell storing a bit having the value 1. In relation to the example presently under consideration, in which the erased memory cells in each case store a bit having the value 0, this means that, as a result of the programming, it is only possible for a bit having the value 1 to be written to a memory cell storing a bit having the value 0. By contrast, in the example under consideration it is not possible to write a bit having the value 0 to a memory cell storing a bit having the value 1 by programming. If, in the example under consideration, a bit having the value 0 is intended to be written to a memory cell storing a bit having the value 1, this can only be effected by erasing the relevant memory cell. This is the reason why flash memories are generally erased prior to programming.
If the content of a memory transistor is intended to be read out, specific voltages are applied to this memory transistor via the word line, the bit line and the source line to which it is connected, and the current flowing via the relevant bit line is determined, the content of the memory cell formed by the memory transistor being evident from the current flowing via the bit line. The currents flowing via the assigned bit lines BL1 to BLn during the read-out from memory cells are evaluated by the sense amplifiers SA1 to SAn.
The voltages which are applied during the read-out of a memory cell to the memory transistor forming this memory cell, to put it more precisely to the gate terminal, the source terminal and the drain terminal of this transistor, are dimensioned such that the memory transistor is thereby put into the on state if it is erased, and that it remains turned off if it is programmed (or vice versa).
The way in which a memory cell has to be driven during erasure, programming and read-out is known and does not require more detailed explanation.
The memory cell array is generally subdivided into a multiplicity of pages, each page comprising a multiplicity of memory-cells. In the example under consideration, a page is formed by a memory cell row. However, provision could also be made for each page to comprise only part of a memory cell row. It is also possible for a page to comprise only a single memory cell. Independently of this it is also possible for the memory cell array to comprise only a single page.
The memory cell array is programmed page by page. That is to say that all the memory cells of a page can in each case be programmed simultaneously. Which memory cells of a page are actually programmed in each case depends, however, on the data to be written to the memory cells.
The erasure and read-out of the memory cells may likewise be effected page by page, but this is less likely to be the case. Usually, the memory cells that can be read simultaneously and the memory cells that can be erased simultaneously are not identical with the memory cells of one page and can be defined independently of one another.
In order that, during the read-out of a memory cell, a correct decision can be made as to whether the bit stored therein has the level 0 or the level 1, the threshold voltages of the erased memory transistors and the threshold voltages of the programmed memory transistors must differ distinctly from one another. As has already been mentioned above, the threshold voltage of a memory transistor is the difference between the voltage applied to the source terminal and the voltage applied to the gate terminal, from which the memory transistor undergoes transition from the off state to the on state or from the on state to the off state. As has likewise already been mentioned above, the threshold voltage depends, inter alia, on the number of free electrons present in the floating gate. The number of electrons present in the floating gate in turn may be altered by erasure or by programming of the memory transistor. However, it is not the case that all erased memory transistors and all programmed memory transistors each have the same threshold voltage. This is illustrated in FIG. 2.
FIG. 2 shows how many memory cells of a memory device having a multiplicity of memory cells have what threshold voltage. The threshold voltages present are distributed between two ranges, namely a first range B1, which lies between a threshold voltage VT1 and a threshold voltage VT2, and a second range B2, which lies above a threshold voltage VT3, in which case it holds true that VT3>VT2>VT1, and VT1>0.
The threshold voltages of the erased memory transistors lie in the first range B1, and the threshold voltages of the programmed memory transistors lie in the second range B2.
The third range B3 lying between the first range B1 and the second range B2 is a forbidden range in which no threshold voltages are permitted. The difference between the source voltage and the gate voltage which are applied to the respective memory transistors during the read-out thereof lies in said range B3. The use of source and gate voltages having a difference that lies in the range B3 has the effect that the erased memory transistors and the non-erased memory transistors behave differently during the read-out thereof. To put it more precisely, it is the case that the erased memory transistors are in the on state during the read-out thereof, whereas the programmed memory transistors are in the off state during the read-out thereof. The consequence of this is that a relatively large current flows via the bit lines connected to erased memory transistors during the read-out thereof, and that a smaller current or no current flows via the bit lines connected to programmed memory transistors during the read-out thereof. The sense amplifiers SA1 to SAn already mentioned above detect the currents flowing via the bit lines during read-out and can unequivocably ascertain on the basis of the magnitude of these currents whether the memory transistors read are erased or programmed memory transistors.
In order for this to function reliably under all circumstances, the third range B3 must be as large as possible. That is to say that the threshold voltage of that memory transistor which has the highest threshold voltage among the erased memory transistors should be as small as possible, and the threshold voltage of that memory transistor which has the smallest threshold voltage among the programmed memory transistors should be as large as possible. On the other hand, however, it is the case that the threshold voltages of the erased memory transistors are not permitted to be too small either. They are not permitted to fall below a specific known lower limit, because otherwise the memory transistor enters into the normally on state and, consequently, would supply a current contribution during the read-out of a memory cell situated in the same column but in a different row, which may lead to an incorrect read-out of the memory cell to be read. Independently of this, it is furthermore the case that the ranges B1 and B2 are also not permitted to be separated too much from one another, because otherwise it would be necessary to work with particularly high voltages during erasure and during programming of the memory transistors, or every erasure or programming of a memory transistor would have to encompass a plurality of erasure or programming operations.
One possibility for ensuring that programmed memory transistors are reliably identified as programmed during the read-out thereof consists in a programming verification being carried out directly after the programming of a page, which programming verification involves checking whether the programmed memory cells were programmed properly (sufficiently intensely) and by reprogramming those memory transistors which were not programmed properly (not programmed sufficiently intensely) by the programming.
An apparatus that can be used to realize this is shown in FIG. 3.
The arrangement shown in FIG. 3 contains a memory cell array SZF, a multiplicity of sense amplifiers, of which only a single sense amplifier SAx is illustrated for the sake of clarity, a page memory PB, and a control device CL, the control device containing a write data memory WDM, a multiplicity of combination devices, of which only a single combination device CMx is illustrated for the sake of clarity, and a series of further components, which are not shown in FIG. 3, however.
In the example under consideration, the memory cell array SZF is the memory cell array SZF shown in FIG. 1 and described with reference thereto.
The sense amplifiers correspond to the sense amplifiers SA1 to SAn of the arrangement shown in FIG. 1. In the example under consideration, the number of sense amplifiers is equal to the number of memory cells per page. To put it more precisely, each of the memory cells that can be written to and can be erased simultaneously is assigned a dedicated sense amplifier.
The write data memory WDM and the page memory PB serve for buffer-storing the data to be written to the memory cell array SZF and each have a number of memory elements corresponding to the number of memory cells per page. Each memory cell of a page is assigned a dedicated memory element of the write data memory WDM.
The data to be written to the memory cell array are written to the page memory PB before data are written to the memory cell array SZF by the control device CL. The content of the page memory PB can furthermore be modified by the combination devices CM. For this purpose, the page memory PB is connected to the output terminals of the combination devices on the input side. Furthermore, the page memory PB is connected to the bit lines on the output side. Via this connection, the bit line voltage required for programming or non-programming is applied to the bit lines during the programming of the memory cells connected thereto. In this case, the fact of whether the bit line voltage required for programming is applied to the bit line or the bit line voltage required for non-programming is applied to the bit line depends on the data stored in the page memory PB.
In the example under consideration, the number of combination devices CM is likewise equal to the number of memory cells per page. To put it more precisely, each sense amplifier is assigned a dedicated combination device.
Each combination device has two input terminals and an output terminal. Of the input terminals, one input terminal in each case is connected to the output terminal of the assigned sense amplifier. The other input terminal is connected to the memory element of the write data memory WDM which stores the data bit which is to be written to the memory cell which is read by the sense amplifier assigned to the combination device. The output terminal of each combination device is connected to the page memory PB. To put it more precisely, each combination device is connected to the memory element of the page memory PB which stores the data bit which is to be written to the memory cell which is read by the sense amplifier assigned to the combination device. The data output by the combination device are written to the page memory PB. The function and the operating procedure of the combination devices emerge from the following description of the programming of the memory cell array SZF.
If a component of the system containing the memory cell array SZF would like to write data to the memory cell array, to put it more precisely would like to write to a page of the memory cell array, the relevant component communicates to the control device corresponding control commands and also the data to be written to the memory cell array and the address under which these data are to be stored.
The data to be written to the memory cell array are buffer-stored in the write data memory WDM and in the page memory PB. The control device CL then generally instigates firstly an erasure operation, which erases the memory cells of the page to which the new data are to be written. This has the effect that data bits having the value 0 are then stored in all the memory cells of the relevant page. Afterward, the data stored in the page memory PB are written to the page to be written to. In this case, the procedure is such that only those memory cells to which a data bit having the value 1 is intended to be written in accordance with the data stored in the page memory PB are programmed. For the remaining memory cells, that is to say for those memory cells to which a data bit having the value 0 is intended to be written in accordance with the data stored in the page memory PB, no action is performed which alters the charge state of the floating gate thereof.
A check is subsequently made to determine whether the data just written to the memory device match the data actually stored in the relevant memory cells. For this purpose, the memory cells of the page just written to are read, and the data read out are fed to the combination devices CM, which combine said data with the (desired) data stored in the write data memory WDM.
The combination devices CM carry out a combination of the data fed to them such that                the output result is a data bit having the level 0,        if the memory cell read by the assigned sense amplifier SA should not be programmed (have the value 0 written to it), that is to say the data bit fed to the combination device CM from the write data memory WDM has the value 0, or        if the memory cell read by the assigned sense amplifier SA should be programmed (have the value 1 written to it), and the programming was successful, that is to say if the data bit fed to the combination device CM from the write data memory WDM has the value 1 and the data bit read out by the assigned sense amplifier likewise has the value 1, and        the output result is a data bit having the level 1,        if the memory cell read by the assigned sense amplifier should be programmed (have the value 1 written to it), and the programming was unsuccessful, that is to say if the data bit fed to the combination device CM from the write data memory WDM has the value 1 and the data bit read out by the assigned sense amplifier SA has the value 0, however.        
The bits output by the combination devices CM are written to the page memory PB. Ideally, all zeros are then stored in the page memory PB. This would mean that the current content of the page written to previously matches the data to be written to said page and the programming operation can be terminated. If, on the other hand, one or more ones are stored in the page memory, this means that the programming of the page was unsuccessful, to put it more precisely that those memory cells of the memory cell array which are assigned the ones in the page memory were not written to properly. The programming operation is repeated in this case. Here, however, only those memory cells of the memory cell array which were not programmed successfully are reprogrammed.
An apparatus approximately corresponding to the arrangement shown in FIG. 3 is disclosed in EP 0 801 795 B1. Another possibility for identifying and handling programming errors is disclosed in EP 1 073 065 A1.
The reprogramming of the unsuccessfully programmed memory cells makes it possible for these memory cells also to be programmed properly. However, this advantage has to be bought at the cost of a very high additional outlay. In particular, it is necessary to provide a multiplicity of combination devices and a bus that connects the combination devices and the page memory. This has the effect that the arrangement shown in FIG. 3 is considerably larger and more expensive than an arrangement in which the programming is not checked and repeated. Furthermore, in particular the combinations carried out by the combination devices are very time-consuming, which leads to a not inconsiderable delay of the erasure or programming.
Corresponding problems also occur with other types of nonvolatile memory devices.
Furthermore, in the case of nonvolatile memory devices, the problem can also arise that memory cells to be erased were not erased properly.